#line 1 "ad_x86_misc.cpp"
//
// Copyright (c) 2003, 2017, Oracle and/or its affiliates. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This code is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License version 2 only, as
// published by the Free Software Foundation.
//
// This code is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// version 2 for more details (a copy is included in the LICENSE file that
// accompanied this code).
//
// You should have received a copy of the GNU General Public License version
// 2 along with this work; if not, write to the Free Software Foundation,
// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
//
// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
// or visit www.oracle.com if you need additional information or have any
// questions.
//
//

// Machine Generated File.  Do Not Edit!

#include "precompiled.hpp"
#include "adfiles/ad_x86.hpp"
const RegMask &loadBNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &loadB2LNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &loadUBNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &loadUB2LNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &loadUB2L_immINode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &loadSNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &loadS2BNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &loadS2LNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &loadUSNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &loadUS2BNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &loadUS2LNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &loadUS2L_immI_255Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &loadUS2L_immINode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &loadINode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &loadI2BNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &loadI2UBNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &loadI2SNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &loadI2USNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &loadI2LNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &loadI2L_immI_255Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &loadI2L_immI_65535Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &loadI2L_immU31Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &loadUI2LNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &loadLNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &loadRangeNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &loadPNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &loadNNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &loadKlassNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &loadNKlassNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &loadFNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &MoveF2VLNode::out_RegMask() const { return (FLOAT_REG_VL_mask()); }
const RegMask &MoveF2LEGNode::out_RegMask() const { return (FLOAT_REG_LEGACY_mask()); }
const RegMask &MoveVL2FNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &MoveLEG2FNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &loadD_partialNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &loadDNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &MoveD2VLNode::out_RegMask() const { return (DOUBLE_REG_VL_mask()); }
const RegMask &MoveD2LEGNode::out_RegMask() const { return (DOUBLE_REG_LEGACY_mask()); }
const RegMask &MoveVL2DNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &MoveLEG2DNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &maxF_regNode::out_RegMask() const { return (FLOAT_REG_LEGACY_mask()); }
const RegMask &maxF_reduction_regNode::out_RegMask() const { return (FLOAT_REG_LEGACY_mask()); }
const RegMask &maxD_regNode::out_RegMask() const { return (DOUBLE_REG_LEGACY_mask()); }
const RegMask &maxD_reduction_regNode::out_RegMask() const { return (DOUBLE_REG_LEGACY_mask()); }
const RegMask &minF_regNode::out_RegMask() const { return (FLOAT_REG_LEGACY_mask()); }
const RegMask &minF_reduction_regNode::out_RegMask() const { return (FLOAT_REG_LEGACY_mask()); }
const RegMask &minD_regNode::out_RegMask() const { return (DOUBLE_REG_LEGACY_mask()); }
const RegMask &minD_reduction_regNode::out_RegMask() const { return (DOUBLE_REG_LEGACY_mask()); }
const RegMask &leaP8Node::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &leaP32Node::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &leaPIdxOffNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &leaPIdxScaleNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &leaPPosIdxScaleNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &leaPIdxScaleOffNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &leaPPosIdxOffNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &leaPPosIdxScaleOffNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &leaPCompressedOopOffsetNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &leaP8NarrowNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &leaP32NarrowNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &leaPIdxOffNarrowNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &leaPIdxScaleNarrowNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &leaPIdxScaleOffNarrowNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &leaPPosIdxOffNarrowNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &leaPPosIdxScaleOffNarrowNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &loadConINode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &loadConI0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &loadConLNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &loadConL0Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &loadConUL32Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &loadConL32Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &loadConPNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &loadConP0Node::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &loadConP31Node::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &loadConFNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &loadConN0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &loadConNNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &loadConNKlassNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &loadConF0Node::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &loadConDNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &loadConD0Node::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &loadSSINode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &loadSSLNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &loadSSPNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &loadSSFNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &loadSSDNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &prefetchAllocNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &prefetchAllocNTANode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &prefetchAllocT0Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &prefetchAllocT2Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeBNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeCNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeINode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeLNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storePNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeImmP0Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeImmPNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeNNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeNKlassNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeImmN0Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeImmNNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeImmNKlassNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeImmI0Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeImmINode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeImmL0Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeImmLNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeImmC0Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeImmI16Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeImmB0Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeImmBNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeImmCM0_regNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeImmCM0Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeFNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeF0Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeF_immNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeDNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeD0_immNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeD0Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeSSINode::out_RegMask() const { return ((Compile::current()->FIRST_STACK_mask())); }
const RegMask &storeSSLNode::out_RegMask() const { return ((Compile::current()->FIRST_STACK_mask())); }
const RegMask &storeSSPNode::out_RegMask() const { return ((Compile::current()->FIRST_STACK_mask())); }
const RegMask &storeSSFNode::out_RegMask() const { return ((Compile::current()->FIRST_STACK_mask())); }
const RegMask &storeSSDNode::out_RegMask() const { return ((Compile::current()->FIRST_STACK_mask())); }
const RegMask &bytes_reverse_intNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &bytes_reverse_longNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &bytes_reverse_unsigned_shortNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &bytes_reverse_shortNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &countLeadingZerosINode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &countLeadingZerosI_bsrNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &countLeadingZerosLNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &countLeadingZerosL_bsrNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &countTrailingZerosINode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &countTrailingZerosI_bsfNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &countTrailingZerosLNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &countTrailingZerosL_bsfNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &popCountINode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &popCountI_memNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &popCountLNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &popCountL_memNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &membar_acquireNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &membar_acquire_0Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &membar_acquire_lockNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &membar_releaseNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &membar_release_0Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &membar_release_lockNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &membar_volatileNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &unnecessary_membar_volatileNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &membar_storestoreNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &castX2PNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &castP2XNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &convP2INode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &convN2INode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &encodeHeapOopNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &encodeHeapOop_not_nullNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &decodeHeapOopNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &decodeHeapOop_not_nullNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &encodeKlass_not_nullNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &decodeKlass_not_nullNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &jumpXtnd_offsetNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &jumpXtnd_addrNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &jumpXtndNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &cmovI_regNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &cmovI_regUNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &cmovI_regUCFNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &cmovI_memNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &cmovI_memUNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &cmovI_memUCFNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &cmovN_regNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &cmovN_regUNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &cmovN_regUCFNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &cmovP_regNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &cmovP_regUNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &cmovP_regUCFNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &cmovL_regNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &cmovL_memNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &cmovL_regUNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &cmovL_regUCFNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &cmovL_memUNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &cmovL_memUCFNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &cmovF_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &cmovF_regUNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &cmovF_regUCFNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &cmovD_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &cmovD_regUNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &cmovD_regUCFNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &addI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &addI_rReg_immNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &addI_rReg_memNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &addI_rReg_mem_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &addI_mem_rRegNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &addI_mem_rReg_0Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &addI_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &incI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &incI_memNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &decI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &decI_memNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &leaI_rReg_immINode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &addL_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &addL_rReg_immNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &addL_rReg_memNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &addL_rReg_mem_0Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &addL_mem_rRegNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &addL_mem_rReg_0Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &addL_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &incL_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &incL_memNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &decL_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &decL_memNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &leaL_rReg_immLNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &addP_rRegNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &addP_rReg_immNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &leaP_rReg_immNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &checkCastPPNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &castPPNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &castIINode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &loadPLockedNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &storePConditionalNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &storeIConditionalNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &storeLConditionalNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &compareAndSwapPNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &compareAndSwapP_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &compareAndSwapLNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &compareAndSwapL_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &compareAndSwapINode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &compareAndSwapI_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &compareAndSwapBNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &compareAndSwapB_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &compareAndSwapSNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &compareAndSwapS_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &compareAndSwapNNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &compareAndSwapN_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &compareAndExchangeBNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
const RegMask &compareAndExchangeSNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
const RegMask &compareAndExchangeINode::out_RegMask() const { return (INT_RAX_REG_mask()); }
const RegMask &compareAndExchangeLNode::out_RegMask() const { return (LONG_RAX_REG_mask()); }
const RegMask &compareAndExchangeNNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
const RegMask &compareAndExchangePNode::out_RegMask() const { return (PTR_RAX_REG_mask()); }
const RegMask &xaddB_no_resNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &xaddBNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &xaddS_no_resNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &xaddSNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &xaddI_no_resNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &xaddINode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &xaddL_no_resNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &xaddLNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &xchgBNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &xchgSNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &xchgINode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &xchgLNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &xchgPNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &xchgNNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &absI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &absL_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &subI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &subI_rReg_immNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &subI_rReg_memNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &subI_mem_rRegNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &subI_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &subL_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &subL_rReg_immNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &subL_rReg_memNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &subL_mem_rRegNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &subL_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &subP_rRegNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &negI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &negI_memNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &negL_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &negL_memNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &mulI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &mulI_rReg_immNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &mulI_memNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &mulI_mem_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &mulI_mem_immNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &mulL_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &mulL_rReg_immNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &mulL_memNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &mulL_mem_0Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &mulL_mem_immNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &mulHiL_rRegNode::out_RegMask() const { return (LONG_RDX_REG_mask()); }
const RegMask &divI_rRegNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
const RegMask &divL_rRegNode::out_RegMask() const { return (LONG_RAX_REG_mask()); }
const RegMask &divModI_rReg_divmodNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &divModL_rReg_divmodNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &loadConL_0x6666666666666667Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &mul_hiNode::out_RegMask() const { return (LONG_RDX_REG_mask()); }
const RegMask &sarL_rReg_63Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &sarL_rReg_2Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &divL_10Node::out_RegMask() const { return (LONG_RDX_REG_mask()); }
const RegMask &modI_rRegNode::out_RegMask() const { return (INT_RDX_REG_mask()); }
const RegMask &modL_rRegNode::out_RegMask() const { return (LONG_RDX_REG_mask()); }
const RegMask &salI_rReg_1Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &salI_mem_1Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &salI_rReg_immNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &salI_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &salI_rReg_CLNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &salI_mem_CLNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &sarI_rReg_1Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &sarI_mem_1Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &sarI_rReg_immNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &sarI_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &sarI_rReg_CLNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &sarI_mem_CLNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &shrI_rReg_1Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &shrI_mem_1Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &shrI_rReg_immNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &shrI_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &shrI_rReg_CLNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &shrI_mem_CLNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &salL_rReg_1Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &salL_mem_1Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &salL_rReg_immNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &salL_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &salL_rReg_CLNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &salL_mem_CLNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &sarL_rReg_1Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &sarL_mem_1Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &sarL_rReg_immNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &sarL_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &sarL_rReg_CLNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &sarL_mem_CLNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &shrL_rReg_1Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &shrL_mem_1Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &shrL_rReg_immNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &shrL_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &shrL_rReg_CLNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &shrL_mem_CLNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &i2bNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &i2sNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rolI_rReg_imm1Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rolI_rReg_imm8Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rolI_rReg_CLNode::out_RegMask() const { return (INT_NO_RCX_REG_mask()); }
const RegMask &rolI_rReg_i1Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rolI_rReg_i1_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rolI_rReg_i8Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rolI_rReg_i8_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rolI_rReg_Var_C0Node::out_RegMask() const { return (INT_NO_RCX_REG_mask()); }
const RegMask &rolI_rReg_Var_C0_0Node::out_RegMask() const { return (INT_NO_RCX_REG_mask()); }
const RegMask &rolI_rReg_Var_C32Node::out_RegMask() const { return (INT_NO_RCX_REG_mask()); }
const RegMask &rolI_rReg_Var_C32_0Node::out_RegMask() const { return (INT_NO_RCX_REG_mask()); }
const RegMask &rorI_rReg_imm1Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rorI_rReg_imm8Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rorI_rReg_CLNode::out_RegMask() const { return (INT_NO_RCX_REG_mask()); }
const RegMask &rorI_rReg_i1Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rorI_rReg_i1_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rorI_rReg_i8Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rorI_rReg_i8_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rorI_rReg_Var_C0Node::out_RegMask() const { return (INT_NO_RCX_REG_mask()); }
const RegMask &rorI_rReg_Var_C0_0Node::out_RegMask() const { return (INT_NO_RCX_REG_mask()); }
const RegMask &rorI_rReg_Var_C32Node::out_RegMask() const { return (INT_NO_RCX_REG_mask()); }
const RegMask &rorI_rReg_Var_C32_0Node::out_RegMask() const { return (INT_NO_RCX_REG_mask()); }
const RegMask &rolL_rReg_imm1Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &rolL_rReg_imm8Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &rolL_rReg_CLNode::out_RegMask() const { return (LONG_NO_RCX_REG_mask()); }
const RegMask &rolL_rReg_i1Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &rolL_rReg_i1_0Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &rolL_rReg_i8Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &rolL_rReg_i8_0Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &rolL_rReg_Var_C0Node::out_RegMask() const { return (LONG_NO_RCX_REG_mask()); }
const RegMask &rolL_rReg_Var_C0_0Node::out_RegMask() const { return (LONG_NO_RCX_REG_mask()); }
const RegMask &rolL_rReg_Var_C64Node::out_RegMask() const { return (LONG_NO_RCX_REG_mask()); }
const RegMask &rolL_rReg_Var_C64_0Node::out_RegMask() const { return (LONG_NO_RCX_REG_mask()); }
const RegMask &rorL_rReg_imm1Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &rorL_rReg_imm8Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &rorL_rReg_CLNode::out_RegMask() const { return (LONG_NO_RCX_REG_mask()); }
const RegMask &rorL_rReg_i1Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &rorL_rReg_i1_0Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &rorL_rReg_i8Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &rorL_rReg_i8_0Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &rorL_rReg_Var_C0Node::out_RegMask() const { return (LONG_NO_RCX_REG_mask()); }
const RegMask &rorL_rReg_Var_C0_0Node::out_RegMask() const { return (LONG_NO_RCX_REG_mask()); }
const RegMask &rorL_rReg_Var_C64Node::out_RegMask() const { return (LONG_NO_RCX_REG_mask()); }
const RegMask &rorL_rReg_Var_C64_0Node::out_RegMask() const { return (LONG_NO_RCX_REG_mask()); }
const RegMask &andI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &andI_rReg_imm255Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &andI2L_rReg_imm255Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &andI_rReg_imm65535Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &andI2L_rReg_imm65535Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &andI_rReg_immNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &andI_rReg_memNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &andI_rReg_mem_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &andI_mem_rRegNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &andI_mem_rReg_0Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &andI_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &andnI_rReg_rReg_memNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &andnI_rReg_rReg_mem_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &andnI_rReg_rReg_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &andnI_rReg_rReg_rReg_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &blsiI_rReg_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &blsiI_rReg_rReg_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &blsiI_rReg_memNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &blsiI_rReg_mem_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &blsmskI_rReg_memNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &blsmskI_rReg_mem_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &blsmskI_rReg_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &blsmskI_rReg_rReg_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &blsrI_rReg_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &blsrI_rReg_rReg_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &blsrI_rReg_memNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &blsrI_rReg_mem_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &orI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &orI_rReg_immNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &orI_rReg_memNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &orI_rReg_mem_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &orI_mem_rRegNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &orI_mem_rReg_0Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &orI_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &xorI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &xorI_rReg_im1Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &xorI_rReg_immNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &xorI_rReg_memNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &xorI_rReg_mem_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &xorI_mem_rRegNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &xorI_mem_rReg_0Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &xorI_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &andL_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &andL_rReg_imm255Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &andL_rReg_imm65535Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &andL_rReg_immNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &andL_rReg_memNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &andL_rReg_mem_0Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &andL_mem_rRegNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &andL_mem_rReg_0Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &andL_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &andnL_rReg_rReg_memNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &andnL_rReg_rReg_mem_0Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &andnL_rReg_rReg_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &andnL_rReg_rReg_rReg_0Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &blsiL_rReg_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &blsiL_rReg_rReg_0Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &blsiL_rReg_memNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &blsiL_rReg_mem_0Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &blsmskL_rReg_memNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &blsmskL_rReg_mem_0Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &blsmskL_rReg_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &blsmskL_rReg_rReg_0Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &blsrL_rReg_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &blsrL_rReg_rReg_0Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &blsrL_rReg_memNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &blsrL_rReg_mem_0Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &orL_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &orL_rReg_castP2XNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &orL_rReg_castP2X_0Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &orL_rReg_immNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &orL_rReg_memNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &orL_rReg_mem_0Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &orL_mem_rRegNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &orL_mem_rReg_0Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &orL_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &xorL_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &xorL_rReg_im1Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &xorL_rReg_immNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &xorL_rReg_memNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &xorL_rReg_mem_0Node::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &xorL_mem_rRegNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &xorL_mem_rReg_0Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &xorL_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &convI2BNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &convP2BNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &cmpLTMaskNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &cmpLTMask0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &cadd_cmpLTMaskNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &cadd_cmpLTMask_1Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &cadd_cmpLTMask_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &cadd_cmpLTMask_2Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &and_cmpLTMaskNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &and_cmpLTMask_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &cmpF_cc_regNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &cmpF_cc_reg_CFNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &cmpF_cc_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &cmpF_cc_memCFNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &cmpF_cc_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &cmpF_cc_immCFNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &cmpD_cc_regNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &cmpD_cc_reg_CFNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &cmpD_cc_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &cmpD_cc_memCFNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &cmpD_cc_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &cmpD_cc_immCFNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &cmpF_regNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &cmpF_memNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &cmpF_immNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &cmpD_regNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &cmpD_memNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &cmpD_immNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &roundFloat_nopNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &roundDouble_nopNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &convF2D_reg_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &convF2D_reg_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &convD2F_reg_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &convD2F_reg_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &convF2I_reg_regNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &convF2L_reg_regNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &convD2I_reg_regNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &convD2L_reg_regNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &convI2F_reg_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &convI2F_reg_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &convI2D_reg_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &convI2D_reg_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &convXI2F_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &convXI2D_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &convL2F_reg_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &convL2F_reg_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &convL2D_reg_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &convL2D_reg_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &convI2L_reg_regNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &convI2L_reg_reg_zexNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &convI2L_reg_mem_zexNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &zerox_long_reg_regNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &convL2I_reg_regNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &MoveF2I_stack_regNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &MoveI2F_stack_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &MoveD2L_stack_regNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &MoveL2D_stack_reg_partialNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &MoveL2D_stack_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &MoveF2I_reg_stackNode::out_RegMask() const { return ((Compile::current()->FIRST_STACK_mask())); }
const RegMask &MoveI2F_reg_stackNode::out_RegMask() const { return ((Compile::current()->FIRST_STACK_mask())); }
const RegMask &MoveD2L_reg_stackNode::out_RegMask() const { return ((Compile::current()->FIRST_STACK_mask())); }
const RegMask &MoveL2D_reg_stackNode::out_RegMask() const { return ((Compile::current()->FIRST_STACK_mask())); }
const RegMask &MoveF2I_reg_regNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &MoveD2L_reg_regNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &MoveI2F_reg_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &MoveL2D_reg_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &rep_stosNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &rep_stos_largeNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &string_compareLNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
const RegMask &string_compareUNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
const RegMask &string_compareLUNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
const RegMask &string_compareULNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
const RegMask &string_indexof_conLNode::out_RegMask() const { return (INT_RBX_REG_mask()); }
const RegMask &string_indexof_conUNode::out_RegMask() const { return (INT_RBX_REG_mask()); }
const RegMask &string_indexof_conULNode::out_RegMask() const { return (INT_RBX_REG_mask()); }
const RegMask &string_indexofLNode::out_RegMask() const { return (INT_RBX_REG_mask()); }
const RegMask &string_indexofUNode::out_RegMask() const { return (INT_RBX_REG_mask()); }
const RegMask &string_indexofULNode::out_RegMask() const { return (INT_RBX_REG_mask()); }
const RegMask &string_indexofU_charNode::out_RegMask() const { return (INT_RBX_REG_mask()); }
const RegMask &string_equalsNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
const RegMask &array_equalsBNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
const RegMask &array_equalsCNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
const RegMask &has_negativesNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
const RegMask &string_compressNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
const RegMask &string_inflateNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &encode_iso_arrayNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
const RegMask &overflowAddI_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &overflowAddI_rReg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &overflowAddL_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &overflowAddL_rReg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &overflowSubI_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &overflowSubI_rReg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &overflowSubL_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &overflowSubL_rReg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &overflowNegI_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &overflowNegL_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &overflowMulI_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &overflowMulI_rReg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &overflowMulL_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &overflowMulL_rReg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &compI_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &compI_rReg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &compI_rReg_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &testI_regNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &testI_reg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &testI_reg_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &testI_reg_mem_0Node::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &compU_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &compU_rReg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &compU_rReg_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &testU_regNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &compP_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &compP_rReg_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &compP_mem_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &testP_regNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &testP_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &testP_mem_reg0Node::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &compN_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &compN_rReg_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &compN_rReg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &compN_mem_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &compN_rReg_imm_klassNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &compN_mem_imm_klassNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &testN_regNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &testN_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &testN_mem_reg0Node::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &compL_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &compL_rReg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &compL_rReg_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &testL_regNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &testL_reg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &testL_reg_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &testL_reg_mem_0Node::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &testL_reg_mem2Node::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &testL_reg_mem2_0Node::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &cmpL3_reg_regNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &compUL_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &compUL_rReg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &compUL_rReg_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &testUL_regNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &compB_mem_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &testB_mem_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &cmovI_reg_gNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &minI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &cmovI_reg_lNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &maxI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &jmpDirNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &jmpConNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &jmpLoopEndNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &jmpLoopEndUNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &jmpLoopEndUCFNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &jmpLoopEnd_and_restoreMaskNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &jmpLoopEndU_and_restoreMaskNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &jmpLoopEndUCF_and_restoreMaskNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &jmpConUNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &jmpConUCFNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &jmpConUCF2Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &partialSubtypeCheckNode::out_RegMask() const { return (PTR_RDI_REG_mask()); }
const RegMask &partialSubtypeCheck_vs_ZeroNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &jmpDir_shortNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &jmpCon_shortNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &jmpLoopEnd_shortNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &jmpLoopEndU_shortNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &jmpLoopEndUCF_shortNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &jmpConU_shortNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &jmpConUCF_shortNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &jmpConUCF2_shortNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &cmpFastLockRTMNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &cmpFastLockNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &cmpFastUnlockNode::out_RegMask() const { return (INT_FLAGS_mask()); }
const RegMask &safePoint_pollNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &safePoint_poll_farNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &safePoint_poll_tlsNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &CallStaticJavaDirectNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &CallDynamicJavaDirectNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &CallRuntimeDirectNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &CallLeafDirectNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &CallLeafNoFPDirectNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &RetNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &TailCalljmpIndNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &tailjmpIndNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &CreateExceptionNode::out_RegMask() const { return (PTR_RAX_REG_mask()); }
const RegMask &RethrowExceptionNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &loadBarrierSlowRegNoVecNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &loadBarrierSlowRegXmmAndYmmNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &loadBarrierSlowRegZmmNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &loadBarrierWeakSlowRegNoVecNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &loadBarrierWeakSlowRegXmmAndYmmNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &loadBarrierWeakSlowRegZmmNode::out_RegMask() const { return (PTR_REG_mask()); }
const RegMask &tlsLoadPNode::out_RegMask() const { return (PTR_R15_REG_mask()); }
const RegMask &ShouldNotReachHereNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &setMaskNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &addF_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &addF_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &addF_mem_0Node::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &addF_immNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &addF_reg_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &addF_reg_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &addF_reg_mem_0Node::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &addF_reg_immNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &addD_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &addD_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &addD_mem_0Node::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &addD_immNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &addD_reg_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &addD_reg_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &addD_reg_mem_0Node::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &addD_reg_immNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &subF_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &subF_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &subF_immNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &subF_reg_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &subF_reg_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &subF_reg_immNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &subD_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &subD_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &subD_immNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &subD_reg_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &subD_reg_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &subD_reg_immNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &mulF_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &mulF_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &mulF_mem_0Node::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &mulF_immNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &mulF_reg_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &mulF_reg_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &mulF_reg_mem_0Node::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &mulF_reg_immNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &mulD_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &mulD_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &mulD_mem_0Node::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &mulD_immNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &mulD_reg_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &mulD_reg_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &mulD_reg_mem_0Node::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &mulD_reg_immNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &divF_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &divF_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &divF_immNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &divF_reg_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &divF_reg_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &divF_reg_immNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &divD_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &divD_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &divD_immNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &divD_reg_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &divD_reg_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &divD_reg_immNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &absF_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &absF_reg_regNode::out_RegMask() const { return (FLOAT_REG_VL_mask()); }
const RegMask &absD_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &absD_reg_regNode::out_RegMask() const { return (DOUBLE_REG_VL_mask()); }
const RegMask &negF_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &negF_reg_regNode::out_RegMask() const { return (FLOAT_REG_VL_mask()); }
const RegMask &negD_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &negD_reg_regNode::out_RegMask() const { return (DOUBLE_REG_VL_mask()); }
const RegMask &sqrtF_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &sqrtF_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &sqrtF_immNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &sqrtD_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &sqrtD_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &sqrtD_immNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &roundD_regNode::out_RegMask() const { return (DOUBLE_REG_LEGACY_mask()); }
const RegMask &roundD_memNode::out_RegMask() const { return (DOUBLE_REG_LEGACY_mask()); }
const RegMask &roundD_immNode::out_RegMask() const { return (DOUBLE_REG_LEGACY_mask()); }
const RegMask &vround2D_regNode::out_RegMask() const { return (VECTORX_REG_LEGACY_mask()); }
const RegMask &vround2D_memNode::out_RegMask() const { return (VECTORX_REG_LEGACY_mask()); }
const RegMask &vround4D_regNode::out_RegMask() const { return (VECTORY_REG_LEGACY_mask()); }
const RegMask &vround4D_memNode::out_RegMask() const { return (VECTORY_REG_LEGACY_mask()); }
const RegMask &vround8D_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vround8D_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &onspinwaitNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &fmaD_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &fmaF_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &loadV4Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &MoveVecS2LegNode::out_RegMask() const { return (VECTORS_REG_LEGACY_mask()); }
const RegMask &MoveLeg2VecSNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &loadV8Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &MoveVecD2LegNode::out_RegMask() const { return (VECTORD_REG_LEGACY_mask()); }
const RegMask &MoveLeg2VecDNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &loadV16Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &MoveVecX2LegNode::out_RegMask() const { return (VECTORX_REG_LEGACY_mask()); }
const RegMask &MoveLeg2VecXNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &loadV32Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &MoveVecY2LegNode::out_RegMask() const { return (VECTORY_REG_LEGACY_mask()); }
const RegMask &MoveLeg2VecYNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &loadV64_dwordNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &loadV64_qwordNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &MoveVecZ2LegNode::out_RegMask() const { return (VECTORZ_REG_LEGACY_mask()); }
const RegMask &MoveLeg2VecZNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &storeV4Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeV8Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeV16Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeV32Node::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeV64_dwordNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &storeV64_qwordNode::out_RegMask() const { return (RegMask::Empty); }
const RegMask &Repl16BNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl32BNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl64BNode::out_RegMask() const { return (VECTORZ_REG_LEGACY_mask()); }
const RegMask &Repl16B_immNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl32B_immNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl64B_immNode::out_RegMask() const { return (VECTORZ_REG_LEGACY_mask()); }
const RegMask &Repl4SNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &Repl4S_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &Repl8SNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl8S_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl8S_immNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl16SNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl16S_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl16S_immNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl32SNode::out_RegMask() const { return (VECTORZ_REG_LEGACY_mask()); }
const RegMask &Repl32S_memNode::out_RegMask() const { return (VECTORZ_REG_LEGACY_mask()); }
const RegMask &Repl32S_immNode::out_RegMask() const { return (VECTORZ_REG_LEGACY_mask()); }
const RegMask &Repl4INode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl4I_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl8INode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl8I_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl16INode::out_RegMask() const { return (VECTORZ_REG_LEGACY_mask()); }
const RegMask &Repl16I_memNode::out_RegMask() const { return (VECTORZ_REG_LEGACY_mask()); }
const RegMask &Repl4I_immNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl8I_immNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl16I_immNode::out_RegMask() const { return (VECTORZ_REG_LEGACY_mask()); }
const RegMask &Repl2L_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl4LNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl8LNode::out_RegMask() const { return (VECTORZ_REG_LEGACY_mask()); }
const RegMask &Repl4L_immNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl8L_immNode::out_RegMask() const { return (VECTORZ_REG_LEGACY_mask()); }
const RegMask &Repl4L_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl8L_memNode::out_RegMask() const { return (VECTORZ_REG_LEGACY_mask()); }
const RegMask &Repl2F_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &Repl4F_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl8FNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl8F_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl16FNode::out_RegMask() const { return (VECTORZ_REG_LEGACY_mask()); }
const RegMask &Repl16F_memNode::out_RegMask() const { return (VECTORZ_REG_LEGACY_mask()); }
const RegMask &Repl2F_zeroNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &Repl4F_zeroNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl8F_zeroNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl2D_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl4DNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl4D_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl8DNode::out_RegMask() const { return (VECTORZ_REG_LEGACY_mask()); }
const RegMask &Repl8D_memNode::out_RegMask() const { return (VECTORZ_REG_LEGACY_mask()); }
const RegMask &Repl2D_zeroNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl4D_zeroNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl4BNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &Repl8BNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &Repl4B_immNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &Repl8B_immNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &Repl4B_zeroNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &Repl8B_zeroNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &Repl16B_zeroNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl32B_zeroNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl2SNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &Repl2S_immNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &Repl4S_immNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &Repl2S_zeroNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &Repl4S_zeroNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &Repl8S_zeroNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl16S_zeroNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl2INode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &Repl2I_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &Repl2I_immNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &Repl2I_zeroNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &Repl4I_zeroNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl8I_zeroNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl2LNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl2L_immNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl2L_zeroNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl4L_zeroNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl2FNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &Repl4FNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl2DNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl4B_mem_evexNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &Repl8B_mem_evexNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &Repl16B_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl16B_mem_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl32B_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl32B_mem_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl64B_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &Repl64B_mem_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &Repl16B_imm_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl32B_imm_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl64B_imm_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &Repl64B_zero_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &Repl4S_evexNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &Repl4S_mem_evexNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &Repl8S_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl8S_mem_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl16S_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl16S_mem_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl32S_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &Repl32S_mem_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &Repl8S_imm_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl16S_imm_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl32S_imm_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &Repl32S_zero_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &Repl4I_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl4I_mem_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl8I_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl8I_mem_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl16I_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &Repl16I_mem_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &Repl4I_imm_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl8I_imm_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl16I_imm_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &Repl16I_zero_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &Repl4L_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl8L_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &Repl4L_imm_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl8L_imm_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &Repl2L_mem_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &Repl4L_mem_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl8L_mem_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &Repl8L_zero_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &Repl8F_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl8F_mem_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl16F_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &Repl16F_mem_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &Repl16F_zero_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &Repl4D_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl4D_mem_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &Repl8D_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &Repl8D_mem_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &Repl8D_zero_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &rsadd2I_reduction_regNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rvadd2I_reduction_regNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rvadd2I_reduction_reg_evexNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rsadd4I_reduction_regNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rvadd4I_reduction_regNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rvadd4I_reduction_reg_evexNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rvadd8I_reduction_regNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rvadd8I_reduction_reg_evexNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rvadd16I_reduction_reg_evexNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rvadd2L_reduction_regNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &rvadd4L_reduction_regNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &rvadd8L_reduction_regNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &rsadd2F_reduction_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &rvadd2F_reduction_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &rsadd4F_reduction_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &rvadd4F_reduction_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &radd8F_reduction_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &radd16F_reduction_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &rsadd2D_reduction_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &rvadd2D_reduction_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &rvadd4D_reduction_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &rvadd8D_reduction_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &rsmul2I_reduction_regNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rvmul2I_reduction_regNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rsmul4I_reduction_regNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rvmul4I_reduction_regNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rvmul8I_reduction_regNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rvmul16I_reduction_regNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &rvmul2L_reduction_regNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &rvmul4L_reduction_regNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &rvmul8L_reduction_regNode::out_RegMask() const { return (LONG_REG_mask()); }
const RegMask &rsmul2F_reductionNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &rvmul2F_reduction_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &rsmul4F_reduction_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &rvmul4F_reduction_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &rvmul8F_reduction_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &rvmul16F_reduction_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
const RegMask &rsmul2D_reduction_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &rvmul2D_reduction_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &rvmul4D_reduction_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &rvmul8D_reduction_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
const RegMask &vadd4BNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vadd4B_regNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vadd4B_memNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vadd4B_mem_0Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vadd8BNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vadd8B_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vadd8B_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vadd8B_mem_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vadd16BNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd16B_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd16B_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd16B_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd32B_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vadd32B_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vadd32B_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vadd64B_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vadd64B_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vadd64B_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vadd2SNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vadd2S_regNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vadd2S_memNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vadd2S_mem_0Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vadd4SNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vadd4S_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vadd4S_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vadd4S_mem_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vadd8SNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd8S_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd8S_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd8S_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd16S_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vadd16S_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vadd16S_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vadd32S_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vadd32S_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vadd32S_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vadd2INode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vadd2I_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vadd2I_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vadd2I_mem_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vadd4INode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd4I_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd4I_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd4I_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd8I_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vadd8I_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vadd8I_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vadd16I_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vadd16I_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vadd16I_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vadd2LNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd2L_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd2L_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd2L_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd4L_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vadd4L_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vadd4L_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vadd8L_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vadd8L_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vadd8L_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vadd2FNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vadd2F_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vadd2F_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vadd2F_mem_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vadd4FNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd4F_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd4F_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd4F_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd8F_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vadd8F_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vadd8F_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vadd16F_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vadd16F_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vadd16F_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vadd2DNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd2D_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd2D_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd2D_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vadd4D_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vadd4D_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vadd4D_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vadd8D_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vadd8D_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vadd8D_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vsub4BNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vsub4B_regNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vsub4B_memNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vsub8BNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vsub8B_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vsub8B_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vsub16BNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsub16B_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsub16B_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsub32B_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vsub32B_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vsub64B_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vsub64B_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vsub2SNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vsub2S_regNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vsub2S_memNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vsub4SNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vsub4S_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vsub4S_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vsub8SNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsub8S_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsub8S_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsub16S_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vsub16S_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vsub32S_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vsub32S_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vsub2INode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vsub2I_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vsub2I_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vsub4INode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsub4I_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsub4I_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsub8I_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vsub8I_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vsub16I_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vsub16I_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vsub2LNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsub2L_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsub2L_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsub4L_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vsub4L_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vsub8L_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vsub8L_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vsub2FNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vsub2F_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vsub2F_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vsub4FNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsub4F_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsub4F_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsub8F_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vsub8F_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vsub16F_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vsub16F_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vsub2DNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsub2D_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsub2D_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsub4D_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vsub4D_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vsub8D_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vsub8D_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &mul4B_regNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &mul8B_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &mul16B_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vmul16B_reg_avxNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vmul32B_reg_avxNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vmul64B_reg_avxNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vmul2SNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vmul2S_regNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vmul2S_memNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vmul2S_mem_0Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vmul4SNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vmul4S_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vmul4S_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vmul4S_mem_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vmul8SNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vmul8S_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vmul8S_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vmul8S_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vmul16S_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vmul16S_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vmul16S_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vmul32S_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vmul32S_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vmul32S_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vmul2INode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vmul2I_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vmul2I_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vmul2I_mem_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vmul4INode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vmul4I_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vmul4I_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vmul4I_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vmul2L_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vmul2L_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vmul2L_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vmul4L_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vmul4L_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vmul4L_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vmul8L_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vmul8L_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vmul8L_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vmul8I_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vmul8I_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vmul8I_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vmul16I_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vmul16I_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vmul16I_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vmul2FNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vmul2F_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vmul2F_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vmul2F_mem_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vmul4FNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vmul4F_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vmul4F_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vmul4F_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vmul8F_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vmul8F_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vmul8F_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vmul16F_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vmul16F_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vmul16F_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vmul2DNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vmul2D_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vmul2D_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vmul2D_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vmul4D_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vmul4D_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vmul4D_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vmul8D_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vmul8D_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vmul8D_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vcmov8F_regNode::out_RegMask() const { return (VECTORY_REG_LEGACY_mask()); }
const RegMask &vcmov4D_regNode::out_RegMask() const { return (VECTORY_REG_LEGACY_mask()); }
const RegMask &vdiv2FNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vdiv2F_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vdiv2F_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vdiv4FNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vdiv4F_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vdiv4F_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vdiv8F_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vdiv8F_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vdiv16F_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vdiv16F_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vdiv2DNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vdiv2D_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vdiv2D_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vdiv4D_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vdiv4D_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vdiv8D_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vdiv8D_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vsqrt2D_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsqrt2D_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsqrt4D_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vsqrt4D_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vsqrt8D_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vsqrt8D_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vsqrt2F_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vsqrt2F_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vsqrt4F_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsqrt4F_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsqrt8F_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vsqrt8F_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vsqrt16F_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vsqrt16F_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vshiftcntNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vshiftcnt_0Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vshiftcntimmNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vshift4BNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vshift4B_0Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vshift4B_1Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vshift8BNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vshift8B_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vshift8B_1Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vshift16BNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vshift16B_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vshift16B_1Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vshift16B_avxNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vshift16B_avx_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vshift16B_avx_1Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vshift32B_avxNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vshift32B_avx_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vshift32B_avx_1Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vshift64B_avxNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vshift64B_avx_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vshift64B_avx_1Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vshist2SNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vshist2S_0Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vshist2S_1Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vshift4SNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vshift4S_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vshift4S_1Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vshift8SNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vshift8S_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vshift8S_1Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vshift16SNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vshift16S_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vshift16S_1Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vshift32SNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vshift32S_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vshift32S_1Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vshift2INode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vshift2I_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vshift2I_1Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vshift4INode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vshift4I_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vshift4I_1Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vshift8INode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vshift8I_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vshift8I_1Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vshift16INode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vshift16I_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vshift16I_1Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vshift2LNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vshift2L_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vshift4LNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vshift4L_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vshift8LNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vshift8L_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vshift8L_1Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vsra2L_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsra2L_reg_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vsra4L_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vsra4L_reg_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vand4BNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vand4B_regNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vand4B_memNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vand4B_mem_0Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vand8BNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vand8B_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vand8B_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vand8B_mem_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vand16BNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vand16B_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vand16B_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vand16B_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vand32B_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vand32B_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vand32B_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vand64B_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vand64B_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vand64B_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vor4BNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vor4B_regNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vor4B_memNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vor4B_mem_0Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vor8BNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vor8B_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vor8B_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vor8B_mem_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vor16BNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vor16B_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vor16B_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vor16B_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vor32B_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vor32B_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vor32B_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vor64B_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vor64B_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vor64B_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vxor4BNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vxor4B_regNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vxor4B_memNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vxor4B_mem_0Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vxor8BNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vxor8B_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vxor8B_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vxor8B_mem_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vxor16BNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vxor16B_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vxor16B_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vxor16B_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vxor32B_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vxor32B_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vxor32B_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vxor64B_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vxor64B_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vxor64B_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vabs4B_regNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
const RegMask &vabs8B_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vabs16B_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vabs32B_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vabs64B_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vabs2S_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vabs4S_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vabs8S_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vabs16S_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vabs32S_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vabs2I_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vabs4I_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vabs8I_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vabs16I_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vabs2L_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vabs4L_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vabs8L_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vabsneg2DNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vabsneg2D_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vabsneg4DNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vabsneg4D_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vabsneg8DNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vabsneg8D_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vabsneg2FNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vabsneg2F_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vabsneg4FNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vabsneg4F_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vabsneg8FNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vabsneg8F_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vabsneg16FNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vabsneg16F_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vfma2D_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vfma2D_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vfma4D_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vfma4D_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vfma8D_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vfma8D_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vfma4F_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vfma4F_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vfma8F_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vfma8F_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vfma16F_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vfma16F_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &vpopcount2INode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
const RegMask &vpopcount4INode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
const RegMask &vpopcount8INode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
const RegMask &vpopcount16INode::out_RegMask() const { return (VECTORZ_REG_mask()); }
const RegMask &compareAndSwapP_shenandoahNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &compareAndSwapP_shenandoah_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &compareAndSwapN_shenandoahNode::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &compareAndSwapN_shenandoah_0Node::out_RegMask() const { return (INT_REG_mask()); }
const RegMask &compareAndExchangeN_shenandoahNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
const RegMask &compareAndExchangeP_shenandoahNode::out_RegMask() const { return (PTR_RAX_REG_mask()); }
// Check consistency of C++ compilation with ADLC options:
// Check adlc -DLINUX=1
#ifndef LINUX
#  error "LINUX must be defined"
#endif // LINUX
// Check adlc -D_GNU_SOURCE=1
#ifndef _GNU_SOURCE
#  error "_GNU_SOURCE must be defined"
#endif // _GNU_SOURCE
// Check adlc -DAMD64=1
#ifndef AMD64
#  error "AMD64 must be defined"
#endif // AMD64
// Check adlc -D_LP64=1
#ifndef _LP64
#  error "_LP64 must be defined"
#endif // _LP64
