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Date: Thu, 23 May 2002 15:15:14 +0900
From: Sunagawa Koji / =?ISO-2022-JP?B?GyRCOj1AbhsoQiAbJEI5Jzt5GyhC?= <koj@ofug.net>
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X-Distribute: distribute version 2.1 (Alpha) patchlevel 24e+020417
X-Sequence: FreeBSD-users-jp 68617
Subject: [FreeBSD-users-jp 68617] Dell PowerEdge 8450 and NetGear GA621
Errors-To: owner-FreeBSD-users-jp@jp.FreeBSD.org
Sender: owner-FreeBSD-users-jp@jp.FreeBSD.org
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$B:=@n$G$9!#(B $B$3$s$K$A$O!#(B

2$BE@Js9p$7$^$9!#(B

$B!&(BDell PowerEdge 8450 $B>e$G(B FreeBSD 4.6-RC-20020521-JPSNAP $B$,2TF0$7$^$7$?!#(B
  PowerVault 2205$B$b@\B3$7$F$$$^$9!#(B

$B!&(BNetGear GA621(1000Base-SX$B$J(BNIC)$B$,F0$-$^$7$?!#(B
  http://docs.freebsd.org/cgi/getmsg.cgi?fetch=52144+0+archive/2002/freebsd-net/20020224.freebsd-net
  $B$K$"$k%Q%C%A$r(BFreeBSD 4.6-RC-20020521-JPSNAP$B$K$"$?$k$h$&$K=$@5$7$^$7$?!#(B
  1000Base-SX <--> 100Base-TX $BDL?.$O3NG'$7$^$7$?!#(B 80Mbps$B!A(B90Mbps$B$O=P$F$$$?$O$:(B
  ifconfig nge0 media 1000baseSX mediaopt full-duplex $B$r;XDj$9$kI,MW$"$j!#(B


$B$D$$$G$K<ALd$5$;$F$/$@$5$$!#(B
4GB$BEk:\$7$F$$$k$N$G$9$,!"(Bdmesg$B$K$"$k$h$&$K(B
3.5GB(3758096384)$B$7$+G'<1$7$F$$$^$;$s!#(B
$B2?$r$7$?$i(B4GB$B$P$C$A$j;H$($k$h$&$K$J$k$s$G$7$g$&$+!#(B


$B0J2<$N$h$&$K(Bkernel$B$GL@<($9$k$H!"(Bboot$BESCf$G8G$^$j$^$9!#(B(T_T)

options        MAXMEM="(4*1024*1024)"

boot$B;~$N%a%C%;!<%8$K$h$k$H!"(B512MB$B$[$I(B4GB$B$rD6$($?$+$i(B
$B@Z$j<N$F$k$J$s$F$3$H$,=q$$$F$"$j$^$7$?!#(B
   (524288KB of memory above 4GB ignore)

4GB$BD6$($?J,$r@Z$j<N$F$?$J$i!"(B4GB$BG'<1$7$F$$$k(B
$B$O$:$J$s$G$9$,!"<B:]$K$O(B
real memory  = 3758096384 (3670016K bytes)
avail memory = 3660361728 (3574572K bytes)
$B$H!"(B3.5GB$B$7$+G'<1$7$F$$$^$;$s!#(B

BIOS$B$O(B4GB$BG'<1$7$F$$$k$h$&$G$9!#(B
$B%a%b%j%A%'%C%/$G(B04193280KB$B$H=P$F$$$^$7$?!#(B


http://www.ofug.net/~koj/FreeBSD/NetGear-GA621/PowerEdge8450-GA621-nge.dmesg.txt
http://www.ofug.net/~koj/FreeBSD/NetGear-GA621/patch.if_ngereg.h
http://www.ofug.net/~koj/FreeBSD/NetGear-GA621/patch.if_nge.c

dmesg$B$N7k2L(B
--------------------------------------------------------
Copyright (c) 1992-2002 The FreeBSD Project.
Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
	The Regents of the University of California. All rights reserved.
FreeBSD 4.6-RC-20020521-JPSNAP #1: Wed May 22 07:51:34 JST 2002
    root@XXXXX.jp:/usr/obj/usr/src/sys/HOGE
Timecounter "i8254"  frequency 1193182 Hz
CPU: Pentium III/Pentium III Xeon/Celeron (700.08-MHz 686-class CPU)
  Origin = "GenuineIntel"  Id = 0x6a4  Stepping = 4
  Features=0x383fbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,MMX,FXSR,SSE>
real memory  = 3758096384 (3670016K bytes)
avail memory = 3660361728 (3574572K bytes)
Programming 64 pins in IOAPIC #0
IOAPIC #0 intpin 2 -> irq 0
FreeBSD/SMP: Multiprocessor motherboard
 cpu0 (BSP): apic id:  5, version: 0x00040011, at 0xfee00000
 cpu1 (AP):  apic id:  4, version: 0x00040011, at 0xfee00000
 io0 (APIC): apic id:  0, version: 0x003f0013, at 0xfec00000
Preloaded elf kernel "kernel.old" at 0xc0311000.
Pentium Pro MTRR support enabled
Using $PIR table, 17 entries at 0xc00fdea0
npx0: <math processor> on motherboard
npx0: INT 16 interface
pcib0: <Host to PCI bridge> on motherboard
IOAPIC #0 intpin 59 -> irq 2
IOAPIC #0 intpin 54 -> irq 5
IOAPIC #0 intpin 58 -> irq 10
IOAPIC #0 intpin 18 -> irq 11
IOAPIC #0 intpin 48 -> irq 15
IOAPIC #0 intpin 49 -> irq 16
pci0: <PCI bus> on pcib0
pci0: <unknown card> (vendor=0x0e11, dev=0xa0f7) at 0.0 irq 2
pcib4: <PCI to PCI bridge (vendor=8086 device=b154)> at device 4.0 on pci0
IOAPIC #0 intpin 57 -> irq 17
pci1: <PCI bus> on pcib4
pcib5: <PCI to PCI bridge (vendor=8086 device=b154)> at device 0.0 on pci1
IOAPIC #0 intpin 61 -> irq 18
pci2: <PCI bus> on pcib5
amr0: <AMI MegaRAID> mem 0xf0000000-0xf7ffffff irq 18 at device 0.0 on pci2
amr0: <PERC 3/DC> Firmware 161J, BIOS 3.17, 128MB RAM
pci1: <unknown card> (vendor=0x1077, dev=0x1216) at 1.0 irq 17
nge0: <National Semiconductor Gigabit Ethernet> port 0x1000-0x10ff mem 0xe8004000-0xe8004fff irq 5 at device 5.0 on pci0
nge0: Ethernet address: 00:40:f4:2a:67:33
nge0: Using TBI
nge0:  1000baseSX, 1000baseSX-FDX, auto
sym0: <896> port 0x1100-0x11ff mem 0xe8000000-0xe8001fff,0xe8006400-0xe80067ff irq 10 at device 10.0 on pci0
sym0: No NVRAM, ID 7, Fast-40, LVD, parity checking
sym1: <896> port 0x1200-0x12ff mem 0xe8002000-0xe8003fff,0xe8006800-0xe8006bff irq 11 at device 10.1 on pci0
sym1: No NVRAM, ID 7, Fast-40, LVD, parity checking
pci0: <Cirrus Logic GD5446 SVGA controller> at 12.0 irq 15
isab0: <Intel 82371AB PCI to ISA bridge> at device 15.0 on pci0
isa0: <ISA bus> on isab0
atapci0: <Intel PIIX4 ATA33 controller> port 0x1320-0x132f at device 15.1 on pci0
ata0: at 0x1f0 irq 14 on atapci0
ata1: at 0x170 irq 15 on atapci0
pci0: <Intel 82371AB/EB (PIIX4) USB controller> at 15.2 irq 16
Timecounter "PIIX"  frequency 3579545 Hz
chip0: <Intel 82371AB Power management controller> port 0xcc0-0xccf at device 15.3 on pci0
pci0: <unknown card> (vendor=0x118c, dev=0x1117) at 20.0
pci0: <unknown card> (vendor=0x118c, dev=0x1117) at 20.1
pcib1: <Host to PCI bridge> on motherboard
IOAPIC #0 intpin 44 -> irq 19
pci3: <PCI bus> on pcib1
pci3: <unknown card> (vendor=0x0e11, dev=0xa0f7) at 0.0 irq 2
fxp0: <Intel Pro 10/100B/100+ Ethernet> port 0x3000-0x303f mem 0xf8000000-0xf801ffff,0xf8020000-0xf8020fff irq 19 at device 5.0 on pci3
fxp0: Ethernet address 00:02:b3:9d:31:10
inphy0: <i82555 10/100 media interface> on miibus0
inphy0:  10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
pci3: <unknown card> (vendor=0x8086, dev=0x123d) at 9.0
pcib2: <Host to PCI bridge> on motherboard
pci4: <PCI bus> on pcib2
pci4: <unknown card> (vendor=0x0e11, dev=0xa0f7) at 0.0 irq 2
pcib3: <Host to PCI bridge> on motherboard
pci5: <PCI bus> on pcib3
pci5: <unknown card> (vendor=0x0e11, dev=0xa0f7) at 0.0 irq 2
orm0: <Option ROMs> at iomem 0xc0000-0xc7fff,0xc9800-0xc9fff,0xdc000-0xdffff on isa0
fdc0: <NEC 72065B or clone> at port 0x3f0-0x3f5,0x3f7 irq 6 drq 2 on isa0
fdc0: FIFO enabled, 8 bytes threshold
fd0: <1440-KB 3.5" drive> on fdc0 drive 0
atkbdc0: <Keyboard controller (i8042)> at port 0x60,0x64 on isa0
atkbd0: <AT Keyboard> flags 0x1 irq 1 on atkbdc0
kbd0 at atkbd0
psm0: <PS/2 Mouse> irq 12 on atkbdc0
psm0: model IntelliMouse Explorer, device ID 4
vga0: <Generic ISA VGA> at port 0x3c0-0x3df iomem 0xa0000-0xbffff on isa0
sc0: <System console> at flags 0x100 on isa0
sc0: VGA <16 virtual consoles, flags=0x300>
sio0 at port 0x3f8-0x3ff irq 4 flags 0x10 on isa0
sio0: type 16550A
sio1 at port 0x2f8-0x2ff irq 3 on isa0
sio1: type 16550A
APIC_IO: Testing 8254 interrupt delivery
APIC_IO: routing 8254 via IOAPIC #0 intpin 2
SMP: AP CPU #1 Launched!
acd0: CDROM <CRD-8482B> at ata0-master PIO4
Waiting 5 seconds for SCSI devices to settle
amrd0: <MegaRAID logical drive> on amr0
amrd0: 34678MB (71020544 sectors) RAID 1 (optimal)
amrd1: <MegaRAID logical drive> on amr0
amrd1: 416136MB (852246528 sectors) RAID 5 (optimal)
Mounting root from ufs:/dev/amrd0s1a
nge0: gigabit link up
uhci0: <Intel 82371AB/EB (PIIX4) USB controller> port 0x1300-0x131f irq 16 at device 15.2 on pci0
usb0: <Intel 82371AB/EB (PIIX4) USB controller> on uhci0
usb0: USB revision 1.0
uhub0: Intel UHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub0: 2 ports with 2 removable, self powered
--------------------------------------------------------


/usr/src/sys/dev/nge/if_ngereg.h $B$N%Q%C%A(B
--------------------------------------------------------
*** if_ngereg.h.orig	Mon Apr 22 03:51:59 2002
--- if_ngereg.h	Wed May 22 07:00:19 2002
***************
*** 128,133 ****
--- 128,134 ----
  #define NGE_CFG_PHYINTR_LNK	0x00080000
  #define NGE_CFG_PHYINTR_DUP	0x00100000
  #define NGE_CFG_MODE_1000	0x00400000
+ #define NGE_CFG_TBI_EN		0x01000000
  #define NGE_CFG_DUPLEX_STS	0x10000000
  #define NGE_CFG_SPEED_STS	0x60000000
  #define NGE_CFG_LINK_STS	0x80000000
***************
*** 421,427 ****
  /* TBI BMCR */
  #define NGE_TBIBMCR_RESTART_ANEG	0x00000200
  #define NGE_TBIBMCR_ENABLE_ANEG		0x00001000
! #define NGE_TBIBMCR_LOOPBACK		0x00004000
  
  /* TBI BMSR */
  #define NGE_TBIBMSR_ANEG_DONE	0x00000004
--- 422,428 ----
  /* TBI BMCR */
  #define NGE_TBIBMCR_RESTART_ANEG	0x00000200
  #define NGE_TBIBMCR_ENABLE_ANEG		0x00001000
! #define NGE_TBIBMCR_LOOPBACK		0x00004000 
  
  /* TBI BMSR */
  #define NGE_TBIBMSR_ANEG_DONE	0x00000004
***************
*** 430,435 ****
--- 431,438 ----
  /* TBI ANAR */
  #define NGE_TBIANAR_HDX		0x00000020
  #define NGE_TBIANAR_FDX		0x00000040
+ #define NGE_TBIANAR_PS1		0x00000080
+ #define NGE_TBIANAR_PS2		0x00000100
  #define NGE_TBIANAR_PCAP	0x00000180
  #define NGE_TBIANAR_REMFAULT	0x00003000
  #define NGE_TBIANAR_NEXTPAGE	0x00008000
***************
*** 437,442 ****
--- 440,447 ----
  /* TBI ANLPAR */
  #define NGE_TBIANLPAR_HDX	0x00000020
  #define NGE_TBIANLPAR_FDX	0x00000040
+ #define NGE_TBIANAR_PS1		0x00000080
+ #define NGE_TBIANAR_PS2		0x00000100
  #define NGE_TBIANLPAR_PCAP	0x00000180
  #define NGE_TBIANLPAR_REMFAULT	0x00003000
  #define NGE_TBIANLPAR_NEXTPAGE	0x00008000
***************
*** 657,662 ****
--- 662,669 ----
  	struct callout_handle	nge_stat_ch;
  	SLIST_HEAD(__nge_jfreehead, nge_jpool_entry)	nge_jfree_listhead;
  	SLIST_HEAD(__nge_jinusehead, nge_jpool_entry)	nge_jinuse_listhead;
+ 	u_int8_t		nge_tbi;
+ 	struct ifmedia		nge_ifmedia;
  };
  
  /*
--------------------------------------------------------



/usr/src/sys/dev/nge/if_ngereg.h $B$N%Q%C%A(B
--------------------------------------------------------
*** if_nge.c.orig	Tue May  7 03:48:23 2002
--- if_nge.c	Wed May 22 07:03:47 2002
***************
*** 615,640 ****
  	struct mii_data		*mii;
  
  	sc = device_get_softc(dev);
! 	mii = device_get_softc(sc->nge_miibus);
  
! 	if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
! 		NGE_SETBIT(sc, NGE_TX_CFG,
! 		    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
! 		NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
  	} else {
! 		NGE_CLRBIT(sc, NGE_TX_CFG,
! 		    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
! 		NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
! 	}
  
! 	/* If we have a 1000Mbps link, set the mode_1000 bit. */
! 	if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX ||
! 	    IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
! 		NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
! 	} else {
! 		NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
! 	}
  
  	return;
  }
  
--- 615,669 ----
  	struct mii_data		*mii;
  
  	sc = device_get_softc(dev);
! 	if (sc->nge_tbi){ /* DJA check this */
! 	  
! 		/*
! 		 * BUG: Can't read Link status so assume FDX unless HDX is
! 		 * specified
! 		 */ 
! 		if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
! 		    == IFM_AUTO) {
! 			if (CSR_READ_4(sc, NGE_TBI_ANLPAR) & NGE_TBIANAR_FDX) {
! 				NGE_SETBIT(sc, NGE_TX_CFG,
! 				    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
! 				NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
! 			} else {
! 				NGE_CLRBIT(sc, NGE_TX_CFG,
! 				    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
! 				NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
! 			}
  
! 		} else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 
! 			!= IFM_FDX) {
! 			NGE_CLRBIT(sc, NGE_TX_CFG,
! 			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
! 			NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
! 		} else {
! 			NGE_SETBIT(sc, NGE_TX_CFG,
! 			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
! 			NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
! 		}
  	} else {
! 		mii = device_get_softc(sc->nge_miibus);
  
! 		if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
! 			NGE_SETBIT(sc, NGE_TX_CFG,
! 			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
! 			NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
! 		} else {
! 			NGE_CLRBIT(sc, NGE_TX_CFG,
! 			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
! 			NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
! 		}
  
+ 		/* If we have a 1000Mbps link, set the mode_1000 bit. */
+ 		if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX ||
+ 		    IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
+ 			NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
+ 		} else {
+ 			NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
+ 		}
+ 	}
  	return;
  }
  
***************
*** 788,793 ****
--- 817,823 ----
  	struct nge_softc	*sc;
  	struct ifnet		*ifp;
  	int			unit, error = 0, rid;
+ 	const char		*sep = "";
  
  	s = splimp();
  
***************
*** 947,960 ****
  	 * Do MII setup.
  	 */
  	if (mii_phy_probe(dev, &sc->nge_miibus,
! 	    nge_ifmedia_upd, nge_ifmedia_sts)) {
! 		printf("nge%d: MII without any PHY!\n", sc->nge_unit);
! 		nge_free_jumbo_mem(sc);
! 		bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
! 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
! 		bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
! 		error = ENXIO;
! 		goto fail;
  	}
  
  	/*
--- 977,1024 ----
  	 * Do MII setup.
  	 */
  	if (mii_phy_probe(dev, &sc->nge_miibus,
! 			  nge_ifmedia_upd, nge_ifmedia_sts)) {
! 		if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) {
! 			sc->nge_tbi = 1;
! 			device_printf(dev, "Using TBI\n");
! 			
! 			sc->nge_miibus = dev;
! 
! 			ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd, 
! 				nge_ifmedia_sts);
! #define	ADD(m, c)	ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL)
! #define PRINT(s)	printf("%s%s", sep, s); sep = ", "
! 			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0);
! 			device_printf(dev, " ");
! 			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0);
! 			PRINT("1000baseSX");
! 			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0);
! 			PRINT("1000baseSX-FDX");
! 			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0);
! 			PRINT("auto");
! 	    
! 			printf("\n");
! #undef ADD
! #undef PRINT
! 			ifmedia_set(&sc->nge_ifmedia, 
! 				IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0));
! 	    
! 			CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
! 				| NGE_GPIO_GP4_OUT 
! 				| NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 
! 				| NGE_GPIO_GP3_OUTENB
! 				| NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN);
! 	    
! 		} else {
! 			printf("nge%d: MII without any PHY!\n", sc->nge_unit);
! 			nge_free_jumbo_mem(sc);
! 			bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
! 			bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
! 			bus_release_resource(dev, NGE_RES, NGE_RID, 
! 					 sc->nge_res);
! 			error = ENXIO;
! 			goto fail;
! 		}
  	}
  
  	/*
***************
*** 964,969 ****
--- 1028,1034 ----
  	callout_handle_init(&sc->nge_stat_ch);
  
  fail:
+ 
  	splx(s);
  	return(error);
  }
***************
*** 985,992 ****
  	ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
  
  	bus_generic_detach(dev);
! 	device_delete_child(dev, sc->nge_miibus);
! 
  	bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
  	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
  	bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
--- 1050,1058 ----
  	ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
  
  	bus_generic_detach(dev);
! 	if (!sc->nge_tbi){
! 		device_delete_child(dev, sc->nge_miibus);
! 	}
  	bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
  	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
  	bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
***************
*** 1324,1330 ****
  		cur_rx->nge_mbuf = NULL;
  		total_len = NGE_RXBYTES(cur_rx);
  		NGE_INC(i, NGE_RX_LIST_CNT);
- 
  		/*
  		 * If an error occurs, update stats, clear the
  		 * status word and leave the mbuf cluster in place:
--- 1390,1395 ----
***************
*** 1337,1343 ****
  			continue;
  		}
  
- 
  		/*
  		 * Ok. NatSemi really screwed up here. This is the
  		 * only gigE chip I know of with alignment constraints
--- 1402,1407 ----
***************
*** 1487,1508 ****
  	sc = xsc;
  	ifp = &sc->arpcom.ac_if;
  
! 	mii = device_get_softc(sc->nge_miibus);
! 	mii_tick(mii);
  
! 	if (!sc->nge_link) {
! 		if (mii->mii_media_status & IFM_ACTIVE &&
! 		    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
! 			sc->nge_link++;
! 			if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX)
! 				printf("nge%d: gigabit link up\n",
! 				    sc->nge_unit);
! 			if (ifp->if_snd.ifq_head != NULL)
! 				nge_start(ifp);
  		}
  	}
- 	sc->nge_stat_ch = timeout(nge_tick, sc, hz);
- 
  
  	splx(s);
  
--- 1551,1586 ----
  	sc = xsc;
  	ifp = &sc->arpcom.ac_if;
  
! 	if (sc->nge_tbi){
! 		if (!sc->nge_link) {
! 			if (CSR_READ_4(sc, NGE_TBI_BMSR) 
! 			    & NGE_TBIBMSR_ANEG_DONE){
!   				printf("nge%d: gigabit link up\n",
!   				    sc->nge_unit);
! 				nge_miibus_statchg(sc->nge_miibus);
! 				sc->nge_link++;
! 				if (ifp->if_snd.ifq_head != NULL)
! 					nge_start(ifp);
! 			} else
! 				sc->nge_stat_ch = timeout(nge_tick, sc, hz);
! 		}
! 	} else {
! 		mii = device_get_softc(sc->nge_miibus);
! 		mii_tick(mii);
  
! 		if (!sc->nge_link) {
! 			if (mii->mii_media_status & IFM_ACTIVE &&
! 			    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
! 				sc->nge_link++;
! 				if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX)
! 					printf("nge%d: gigabit link up\n",
! 					    sc->nge_unit);
! 				if (ifp->if_snd.ifq_head != NULL)
! 					nge_start(ifp);
! 			}
  		}
+ 		sc->nge_stat_ch = timeout(nge_tick, sc, hz);
  	}
  
  	splx(s);
  
***************
*** 1528,1533 ****
--- 1606,1616 ----
  	/* Disable interrupts. */
  	CSR_WRITE_4(sc, NGE_IER, 0);
  
+ 	/* Data LED on for TBI mode */
+ 	if(sc->nge_tbi)
+ 		 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
+ 			     | NGE_GPIO_GP3_OUT);
+ 
  	for (;;) {
  		/* Reading the ISR register clears all interrupts. */
  		status = CSR_READ_4(sc, NGE_ISR);
***************
*** 1573,1578 ****
--- 1656,1667 ----
  	if (ifp->if_snd.ifq_head != NULL)
  		nge_start(ifp);
  
+ 	/* Data LED off for TBI mode */
+ 
+ 	if(sc->nge_tbi)
+ 		CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
+ 			    & ~NGE_GPIO_GP3_OUT);
+ 
  	return;
  }
  
***************
*** 1724,1730 ****
  	nge_stop(sc);
  	sc->nge_stat_ch = timeout(nge_tick, sc, hz);
  
! 	mii = device_get_softc(sc->nge_miibus);
  
  	/* Set MAC address */
  	CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
--- 1813,1823 ----
  	nge_stop(sc);
  	sc->nge_stat_ch = timeout(nge_tick, sc, hz);
  
! 	if (sc->nge_tbi){
! 		mii = NULL;
! 	} else {
! 		mii = device_get_softc(sc->nge_miibus);
! 	}
  
  	/* Set MAC address */
  	CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
***************
*** 1822,1838 ****
  	 */
  	NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
  
- 	/* Set full/half duplex mode. */
- 	if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
- 		NGE_SETBIT(sc, NGE_TX_CFG,
- 		    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
- 		NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
- 	} else {
- 		NGE_CLRBIT(sc, NGE_TX_CFG,
- 		    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
- 		NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
- 	}
- 
  	/*
  	 * Enable the delivery of PHY interrupts based on
  	 * link/speed/duplex status changes. Also enable the
--- 1915,1920 ----
***************
*** 1881,1895 ****
  
  	sc = ifp->if_softc;
  
! 	mii = device_get_softc(sc->nge_miibus);
! 	sc->nge_link = 0;
! 	if (mii->mii_instance) {
! 		struct mii_softc	*miisc;
! 		for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
! 		    miisc = LIST_NEXT(miisc, mii_list))
! 			mii_phy_reset(miisc);
  	}
- 	mii_mediachg(mii);
  
  	return(0);
  }
--- 1963,2007 ----
  
  	sc = ifp->if_softc;
  
! 	if (sc->nge_tbi){
! 		if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 
! 		     == IFM_AUTO) {
! 			CSR_WRITE_4(sc, NGE_TBI_ANAR, 
! 				CSR_READ_4(sc, NGE_TBI_ANAR)
! 					| NGE_TBIANAR_HDX | NGE_TBIANAR_FDX);
! 			CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG
! 				| NGE_TBIBMCR_RESTART_ANEG);
! 			CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG);
! 		} else if ((sc->nge_ifmedia.ifm_cur->ifm_media 
! 			    & IFM_GMASK) == IFM_FDX) {
! 			NGE_SETBIT(sc, NGE_TX_CFG,
! 			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
! 			NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
! 
! 			CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
! 			CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
! 		} else {
! 			NGE_CLRBIT(sc, NGE_TX_CFG,
! 			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
! 			NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
! 
! 			CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
! 			CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
! 		}
! 			
! 		CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
! 			    & ~NGE_GPIO_GP3_OUT);
! 	} else {
! 		mii = device_get_softc(sc->nge_miibus);
! 		sc->nge_link = 0;
! 		if (mii->mii_instance) {
! 			struct mii_softc	*miisc;
! 			for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
! 			    miisc = LIST_NEXT(miisc, mii_list))
! 				mii_phy_reset(miisc);
! 		}
! 		mii_mediachg(mii);
  	}
  
  	return(0);
  }
***************
*** 1906,1915 ****
  
  	sc = ifp->if_softc;
  
! 	mii = device_get_softc(sc->nge_miibus);
! 	mii_pollstat(mii);
! 	ifmr->ifm_active = mii->mii_media_active;
! 	ifmr->ifm_status = mii->mii_media_status;
  
  	return;
  }
--- 2018,2067 ----
  
  	sc = ifp->if_softc;
  
! 	if (sc->nge_tbi){ /* DJA */
! 		ifmr->ifm_status = IFM_AVALID;
! 		ifmr->ifm_active = IFM_ETHER;
! 
! 		/*
! printf("NGE_TBI_BMCR   %x\n",CSR_READ_4(sc, NGE_TBI_BMCR));
! printf("NGE_TBI_BMSR   %x\n",CSR_READ_4(sc, NGE_TBI_BMSR));
! printf("NGE_TBI_ANAR   %x\n",CSR_READ_4(sc, NGE_TBI_ANAR));
! printf("NGE_TBI_ANLPAR %x\n",CSR_READ_4(sc, NGE_TBI_ANLPAR));
! printf("NGE_TBI_ANER   %x\n",CSR_READ_4(sc, NGE_TBI_ANER));
! printf("NGE_TBI_ESR    %x\n",CSR_READ_4(sc, NGE_TBI_ESR));
! 		*/
! 
! 		if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE){
! 			ifmr->ifm_status |= IFM_ACTIVE;
! 		} 
! 		if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK)
! 			ifmr->ifm_active |= IFM_LOOP;
! 		if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE){
! 			ifmr->ifm_active |= IFM_NONE;
! 			ifmr->ifm_status = 0;
! 			return;
! 		} 
! 		ifmr->ifm_active |= IFM_1000_SX;
! 		if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 
! 		    == IFM_AUTO)
! 		  ifmr->ifm_active |= IFM_AUTO;		  
! 		  if (CSR_READ_4(sc, NGE_TBI_ANLPAR) & NGE_TBIANAR_FDX){
! 			ifmr->ifm_active |= IFM_FDX;
! 		  }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR) & NGE_TBIANAR_HDX){
! 			ifmr->ifm_active |= IFM_HDX;
! 		  }
! 		else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 
! 			== IFM_FDX)
! 			ifmr->ifm_active |= IFM_FDX;
! 		else
! 			ifmr->ifm_active |= IFM_HDX;
!  
! 	} else {
! 		mii = device_get_softc(sc->nge_miibus);
! 		mii_pollstat(mii);
! 		ifmr->ifm_active = mii->mii_media_active;
! 		ifmr->ifm_status = mii->mii_media_status;
! 	}
  
  	return;
  }
***************
*** 1981,1988 ****
  		break;
  	case SIOCGIFMEDIA:
  	case SIOCSIFMEDIA:
! 		mii = device_get_softc(sc->nge_miibus);
! 		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
  		break;
  	default:
  		error = EINVAL;
--- 2133,2146 ----
  		break;
  	case SIOCGIFMEDIA:
  	case SIOCSIFMEDIA:
! 		if (sc->nge_tbi){ /* DJA */
! 			error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia, 
! 					      command);
! 		} else{
! 			mii = device_get_softc(sc->nge_miibus);
! 			error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 
! 					      command);
! 		}
  		break;
  	default:
  		error = EINVAL;
***************
*** 2030,2036 ****
  
  	ifp = &sc->arpcom.ac_if;
  	ifp->if_timer = 0;
! 	mii = device_get_softc(sc->nge_miibus);
  
  	untimeout(nge_tick, sc, sc->nge_stat_ch);
  	CSR_WRITE_4(sc, NGE_IER, 0);
--- 2188,2198 ----
  
  	ifp = &sc->arpcom.ac_if;
  	ifp->if_timer = 0;
! 	if (sc->nge_tbi){
! 		mii = NULL;
! 	} else {
! 		mii = device_get_softc(sc->nge_miibus);
! 	}
  
  	untimeout(nge_tick, sc, sc->nge_stat_ch);
  	CSR_WRITE_4(sc, NGE_IER, 0);
***************
*** 2047,2056 ****
  	 */
  	itmp = ifp->if_flags;
  	ifp->if_flags |= IFF_UP;
! 	ifm = mii->mii_media.ifm_cur;
  	mtmp = ifm->ifm_media;
  	ifm->ifm_media = IFM_ETHER|IFM_NONE;
! 	mii_mediachg(mii);
  	ifm->ifm_media = mtmp;
  	ifp->if_flags = itmp;
  
--- 2209,2225 ----
  	 */
  	itmp = ifp->if_flags;
  	ifp->if_flags |= IFF_UP;
! 
! 	if (sc->nge_tbi)
! 		ifm = sc->nge_ifmedia.ifm_cur;
! 	else
! 		ifm = mii->mii_media.ifm_cur;
! 	
  	mtmp = ifm->ifm_media;
  	ifm->ifm_media = IFM_ETHER|IFM_NONE;
! 	
! 	if (!sc->nge_tbi)
! 		mii_mediachg(mii);
  	ifm->ifm_media = mtmp;
  	ifp->if_flags = itmp;
  
--------------------------------------------------------

---
($BM-(B)$B%5%$%*%s%3%_%e%K%1!<%7%g%s%:(B
   $B:=@n(B $B9';y(B   koj@syon.co.jp    http://www.syon.co.jp/


